A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture

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An energy efficient deep neural network (DNN) learning processor is proposed using direct feedback alignment (DFA). The proposed processor achieves 2.2 × faster learning speed compared with the previous learning processors by the pipelined DFA (PDFA). In order to enhance the energy efficiency by 38.7%, the heterogeneous learning core (LC) architecture is optimized with the 11-stage pipeline data-path. Furthermore, direct error propagation core (DEPC) utilizes random number generators (RNG) to remove external memory access (EMA) caused by error propagation (EP) and improve the energy efficiency by 19.9%. The proposed PDFA based learning processor is evaluated on the object tracking (OT) application, and as a result, it shows 34.4 frames-per-second (FPS) throughput with 1.32 TOPS/W energy efficiency.
Publisher
Institute of Electrical and Electronics Engineers Inc.
Issue Date
2019-06
Language
English
Citation

33rd Symposium on VLSI Circuits, VLSI Circuits 2019, pp.C304 - C305

DOI
10.23919/VLSIC.2019.8778006
URI
http://hdl.handle.net/10203/268706
Appears in Collection
EE-Conference Papers(학술회의논문)
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