DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hwang, Seokha | ko |
dc.contributor.author | Moon, Seungsik | ko |
dc.contributor.author | Jung, Jaehwan | ko |
dc.contributor.author | Kim, Daesung | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.contributor.author | Ha, Jeongseok | ko |
dc.contributor.author | Lee, Youngjoo | ko |
dc.date.accessioned | 2019-11-26T01:20:05Z | - |
dc.date.available | 2019-11-26T01:20:05Z | - |
dc.date.created | 2019-10-28 | - |
dc.date.created | 2019-10-28 | - |
dc.date.created | 2019-10-28 | - |
dc.date.created | 2019-10-28 | - |
dc.date.issued | 2019-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268556 | - |
dc.description.abstract | Recently, symmetric block-wise concatenated-BCH (SBC-BCH) codes are proposed as strong error-correcting codes (ECCs) based on hard-decision channel outputs, which is especially suited for storages using NAND flash memories. Targeting energy-efficient NAND flash memory applications, this paper presents an energy-optimized decoder architecture which includes an iterative decoder for a SBC-BCH code as a main decoder and a low-complexity auxiliary decoder for a block-wise single parity-check (BSPC) code. The auxiliary decoder is opportunistically in action to break the dominant error bound associated with the SBC-BCH code, which allows one to lower the uncorrectable bit-error-rate (UBER) to 10 -15 in an energy efficient way. This work presents several design-level optimizations for further enhancing the energy-efficiency of the iterative SBC-BCH decoder. More precisely, the new initialization scheme is proposed for ensuring the energy-efficient seamless decoding scenario. The syndrome tracking is applied to eliminate the previous syndrome calculation and the reordered Chien search further enhances the energy-efficiency as well as the decoding throughput. Targeting a 0.9-rate 4KB SBC-BCH code for commercialized storages using NAND flash memories, a prototype decoder consisting of both the iterative main and auxiliary decoders is designed in a 65-nm CMOS process. By applying the proposed optimizations, the prototype decoder achieves an energy-efficiency of 3.43 pJ/b while providing a decoding throughput of 13.2 Gb/s, which is superior to the previous state-of-the-art decoders for mobile storages. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages | - |
dc.type | Article | - |
dc.identifier.wosid | 000494680200032 | - |
dc.identifier.scopusid | 2-s2.0-85070938966 | - |
dc.type.rims | ART | - |
dc.citation.volume | 66 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 4462 | - |
dc.citation.endingpage | 4475 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2019.2922983 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.localauthor | Ha, Jeongseok | - |
dc.contributor.nonIdAuthor | Hwang, Seokha | - |
dc.contributor.nonIdAuthor | Moon, Seungsik | - |
dc.contributor.nonIdAuthor | Jung, Jaehwan | - |
dc.contributor.nonIdAuthor | Kim, Daesung | - |
dc.contributor.nonIdAuthor | Lee, Youngjoo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Decoding | - |
dc.subject.keywordAuthor | Iterative decoding | - |
dc.subject.keywordAuthor | Error correction codes | - |
dc.subject.keywordAuthor | Prototypes | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Encoding | - |
dc.subject.keywordAuthor | Optimization | - |
dc.subject.keywordAuthor | Error correction codes | - |
dc.subject.keywordAuthor | flash memory | - |
dc.subject.keywordAuthor | low-power architecture | - |
dc.subject.keywordAuthor | VLSI | - |
dc.subject.keywordPlus | NAND FLASH MEMORY | - |
dc.subject.keywordPlus | ERROR-CORRECTION | - |
dc.subject.keywordPlus | HIGH-THROUGHPUT | - |
dc.subject.keywordPlus | CODES | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | SSD | - |
dc.subject.keywordPlus | ECC | - |
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