Electronic circuit adjusting timing of clock based on bits of output data from sub-ranging analog-to-digital converter하위 범위의 아날로그/디지털 컨버터로부터의 약간의 출력 데이터에 기초가 된 클럭의 타이밍을 조절하는 전자 회로

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An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string.
Assignee
KAIST
Country
US (United States)
Application Date
2018-11-19
Application Number
16194824
Registration Date
2019-10-22
Registration Number
10454489
URI
http://hdl.handle.net/10203/268351
Appears in Collection
EE-Patent(특허)
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