Impact of Bottom-Gate Biasing on Implant-Free Junctionless Ge-on- Insulator n-MOSFETs

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In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (mu(eff)) of 160 cm(2)/V.s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of mu(eff) by bottom-gate biasing.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-09
Language
English
Article Type
Article
Citation

IEEE ELECTRON DEVICE LETTERS, v.40, no.9, pp.1362 - 1365

ISSN
0741-3106
DOI
10.1109/LED.2019.2931410
URI
http://hdl.handle.net/10203/267506
Appears in Collection
EE-Journal Papers(저널논문)
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