An Improved Symbol-flipping Algorithm for Nonbinary LDPC Codes and Its Application to NAND Flash Memory

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This paper proposes a novel symbol-flipping decoding (SFD) algorithm called decision-symbol reliability-based SFD (DRB-SFD) algorithm for nonbinary low-density parity-check (LDPC) codes aiming to improve the error-rate performances of data storage devices with hard-decision channel outputs, e.g., data storage using NAND flash memory. The proposed algorithm generates the reliability information of decision symbols based on a metric for symbol flipping during iterations instead of soft-decision channel outputs. In addition, it quantizes the reliability information into reliability messages that are exchanged between variable and check nodes. The number of quantization levels is carefully chosen to be the same as the field size of coded symbols, which allows the message exchanges to be performed without the additional signal paths. It is also extensively discussed how to decide parameters in the proposed algorithm in an analytic way. We demonstrate that the proposed algorithm featured with the exchanges of reliability messages provides significant performance improvements over existing SFD algorithms on channels with hard-decision outputs.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-09
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON MAGNETICS, v.55, no.9

ISSN
0018-9464
DOI
10.1109/TMAG.2019.2918985
URI
http://hdl.handle.net/10203/267388
Appears in Collection
EE-Journal Papers(저널논문)
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