Fast timing and power analysis of custom digital circuits

Abstract

however it only focuses on simple designs with a few types of complementary logic gates. Moreover, it only conducts the timing analysis, so the power consumption during the circuit operation cannot be provided. Thus, we propose a method to cover various designs of circuits in timing estimation as well as power estimation method. We convert transistor-level digital circuit netlist into logic gate units, so that we can group the various gates from transistor netlist. Each gate is modeled into HDL modules, which we present to model the function of any gates, in consideration of the effect of switched resistance and capacitance on propagation delay of a gate. The HDL simulation provides the signal transition information on time in value change dump (VCD) file format, so we can estimate the power consumption during the simulation with power models we generated for estimate static and dynamic power consumption of a gate. The power libraries are built for estimate the sub-threshold leakage current to model the static power and energy dissipation due to the capacitive coupling and short-circuit current for calculate the average power consumption. Experimental results show that the proposed method can accelerate the simulation time of timing and power estimation, up to X972, X93. The accuracy of timing and power analysis were reported 11% and 13% on average respectively.

The timing and power analysis of custom digital circuit have to be performed with transistor-level SPICE like simulator, which is too slow to run on the entire circuit. As a fast simulation method, HDL modeling based timing analysis method is proposed