Accurate wirelength prediction for placement driven synthesis through machine learning

Abstract

In sub-10nm technology, interconnect delay takes up an appreciable portion of circuit delay. Interconnect delay, however, cannot be accurately taken into account before placement and routing (P&R), which often causes many design iterations and increases turn around time.

In this thesis, I propose a method of predicting wire length before P&R by using machine learning techniques. Effective parameters are identified and extracted from virtual P&R which is performed in conjunction with logic synthesis and then selected with linear discriminant analysis (LDA) to enhance the prediction accuracy. A model selection method is addressed in this thesis to filter some regression models that are not suitable for wirelength prediction. Multiple regression models are set up after training process, and the best model is chosen for each training sample during validation. After construction of models, we calculate the distance of each training sample to the nearby testing sample in parameter space, identify the training samples within a certain distance to the test sample, and the weight of each model is determined by the ratio of the best model in the identified samples. The final prediction is obtained by weighted sum of predictions in the models. The experiments demonstrate that the proposed method achieves on average of 15% smaller error rate compared to virtual P&R results.