Concatenated codes for NAND flash memory = 낸드 플래시 메모리를 위한 연접 부호

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In this work, we consider high-rate error control systems for storage devices using multi-level per cell (MLC) NAND flash memories. First, we propose a novel design rule of block-wise concatenated Bose-Chaudhuri-Hocquenghem (BC-BCH) codes. BC-BCH codes designed in accordance with the proposed design rule are called quasi-primitive BC-BCH codes in which constituent BCH codes are deliberately chosen for their lengths to be as close to primitive BCH codes as possible. It will be shown that such quasi-primitive BC-BCH codes can achieve significant improvements of error-correcting capability over the existing BC-BCH codes when an iterative hard-decision based decoding (IHDD) is assumed. In addition, we propose a novel collaborative decoding algorithm which targets at resolving dominant error patterns associated with the IHDD. Error-rate performances of error-control systems with the proposed quasi-primitive BC-BCH and existing BC-BCH codes are compared. For more comprehensive performance comparisons, systems with a hypothetically long BCH code and a product code are also considered in the comparisons. Secondly, we consider an error-control system with a hierarchical structure aiming at supporting different sizes of data units when user data are stored in and retrieved from storage devices using NAND flash memories. That is, while encoding is performed for a page of user data, decoding can be carried out for individual access unit level. In addition, when the decoding on the individual access unit level fails, a much stronger error-correcting capability is exerted on the page level by jointly decoding entire access units. A design rule and advantages of the proposed error-control system will be introduced in detail. Comparisons with other error-control systems will also be extensively carried out in terms of error rate, which demonstrates performance superiority of the proposed system over other existing systems. Thirdly, we introduce an error correcting coding scheme called symmetric BC-BCH codes. Symmetric BC-BCH codes have unique features in their structure, i.e. a symmetry and a block-wise concatenation. It will be shown that a careful integration of the symmetry and block-wise concatenation is especially beneficial to achieve improvements of error-rate performance when an iterative decoding algorithm is assumed. For evaluating error-rate performance of symmetric BC-BCH codes, we also develop a semi-analytic performance evaluation technique which is vital to confirm an extremely low target error rate of storage devices. The analysis also elucidates that there are stopping patterns associated with the iterative decoding algorithm in the low error-rate regime. To break the stopping patterns, we will propose a stopping pattern breaking mechanism which further utilizes the structural features in a clever way. Performance comparisons are carried out between error-control systems with a symmetric and quasi-primitive BC-BCH codes, which demonstrate a significant performance improvement of the system with the symmetric BC-BCH code over the one with the previous quasi-primitive BC-BCH code. Finally, we will discuss the channel quantization problem for turbo product codes (TPCs) for practical soft decision based decoding of concatenated codes. While there have been a few previous works on channel quantization for TPCs, they are based on heuristic observations and are not optimized for storage devices using NAND flash memories. Soft decision channel outputs from NAND flash memories are acquired by successive hard decisions which is a costly operation in terms of power consumption and throughput loss. Thus, channel quantization is pivotal to design efficient error-control systems for NAND flash memories. However, to the best of our knowledge, there has not been any previous work related to the quantization problem in the design of error-control systems with TPCs for NAND flash memories. Motivated by this, we developed a quantization scheme which is jointly optimized with TPCs to achieve a better error-correcting capability when the bit precision is limited. In the quantization scheme, the procedure of the soft decision based decoding of BCH codes is carefully considered. Moreover, based on the understandings of the procedure, we also developed a decoding algorithm called modified TPCs which shows drastic error correcting performance improvement from the one with conventional TPCs when the bit precision is limited. In this work, we introduce existing quantization schemes for NAND flash memories and propose a novel quantization scheme and a decoding algorithm.
Advisors
Ha, Jeongseokresearcher하정석researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[vi, 89 p. :]

Keywords

Channel coding▼aerror correcting codes▼aencoding▼adecoding▼aNAND flash memories▼aBCH codes▼ablock-wise concatenation▼aturbo product codes▼aChase decoding algorithm▼areference voltage▼achannel quantization▼amulti-level codes▼ahierarchical codes; 채널 부호▼a오류 정정 부호▼a부호화▼a복호▼a낸드 플래시 메모리▼a비씨에이치 부호▼a블록 단위 연접▼a터보 곱 부호▼a체이스 복호 알고리즘▼a기준 전압▼a채널 양자화▼a다계층 부호▼a계층적 부호

URI
http://hdl.handle.net/10203/265296
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=866977&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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