Transistor leakage considering source/drain extension region = 소스/드레인 영역이 고려된 트랜지스터 누설전류 연구

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As the state-of-the-art transistors go deeply down to the nm-scale dimension, the short-channel effects (SCEs) have become more troublesome than any other period of time. In order to prevent the SCEs as effectively as possible, the multiple-gate and thin channel structures such as the gate-all-around (GAA) nanowire transistors have emerged. Although the state-of-the-art metal oxide field effect transistors (MOSFETs) have obtained more room to be scaled further down to sub-10 nm regime thanks to the better channel controllability achieved by the aforementioned transistor structures, the source/drain (S/D) extension regions were not properly considered in terms of off-state power consumption and on-state drive current. However, the S/D extension regions should also be deserved in the same measure with the channel length because the packing density of an integrated circuit (IC) is decided by the total gate pitch, which is defined as the distance between a transistor and another transistor.Firstly, the vertically stacked nanowire-based inversion-mode (IM) and junctionless-mode (JM) FETs are experimentally studied via their gate-induced drain leakage (GIDL) current. With the aid of technology computer aided design (TCAD)-based numerical simulation results, the source of their difference in GIDL cur-rent is analyzed. Moreover, the effect of the drain extension length on the GAA IM-FET and JM-FET are sys-tematically studied.Furthermore, the device performance of novel types of FETs including the recently proposed charge-plasma FET and the steep-slope tunnel FET (TFET) are analyzed with respect to the S/D extension regions. This research topic is especially important because the two FETs have their unique structures in S/D extension regions, while their S/D extensions have not been appropriately considered in the previous studies.Finally, the extremely scaled-down IM-FET within a double-gate structure is investigated in detail while considering both the band-to-band tunneling and Schottky tunneling effects, in terms of various different device parameters including the S/D extension length, gate length, gate dielectric thickness, S/D doping profile etc.Conclusively, in this dissertation, the effects of aggressively scaled-down S/D extension regions on var-ious types of MOSFETs have been intensively investigated for the first time. Although there have been rigorous efforts on how to reduce the S/D contact resistances from many other groups, this work takes the first step to the research on the general fabrication guideline considering the scaling-down of S/D extension regions. It is expected that this study will shed light on the further scaling-down transistor technology.
Advisors
Choi, Yang-Kyuresearcher최양규researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2019
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.2,[ix, 82 p. :]

Keywords

charge-plasma (C-P) MOSFET▼agate-all-around (GAA)▼agate-induced drain leakage (GIDL)▼ainversion-mode (IM) FET▼ajunctionless-mode (JM) FET▼alongitudinal band-to-band tunneling (L-BTBT)▼anumerical simulation▼aSchottky tunneling▼asource/drain (S/D) extension region▼atunnel FET (TFET); 누설전류▼a소스/드레인 영역▼a샤키 터널링▼a밴드투밴드터널링▼a기들 전류

URI
http://hdl.handle.net/10203/265289
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=842519&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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