(A) study on the design of radiation-tolerant ADC and NED using layout modification technique

Abstract

Space is filled with radiation environments, such as Van Allen belts, solar flares, and galactic cosmic rays. When integrated circuits fabricated in a commercial complementary metal oxide semiconductor (CMOS) pro-cess are exposed to ionizing radiation, they would lose its functionality due to the total ionizing dose (TID) effect. In the first half of the thesis, a 12-bit 40kS/s successive approximation register analog-to-digital converter (ADC) designed with a dummy gate-assisted (DGA) n-MOSFET is presented for space applications requiring high resolution, low power consumption, and moderate conversion speed. The ADC is also designed with a custom-designed metal finger capacitor and a body-tied p-MOSFET protected by guard ring in a bootstrapping circuit to mitigate the performance degradation caused by radiation-induced leakage current. The designed ADC was fab-ricated in a commercial standard 0.35um CMOS process. In order to evaluate its radiation hardness, the fabri-cated ADC was exposed to 60Co gamma rays with a dose of up to 300krad (Si). The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 67.9dB and 78.7dB, respectively. Although a small amount of degradation of the SNDR was observed after radiation exposure, it corresponds to only about a 0.1 effective-number-of-bit (ENOB) drop from the measured result of an unirradiated chip. When electronics are exposed to a high-intensity prompt gamma ray originated from nuclear explosion, a tran-sient or permanent electrical malfunction can be occurred due to the transient radiation effect (TRE). In order to overcome this problem, the nuclear event detector (NED) has been proposed to mitigate the TRE on electronics. The NED detects a prompt gamma ray and quickly switches off any attached systems before they can be dam-aged, with the systems turned back on after the event has passed. In the latter half of the thesis, radiation-tolerant NED signal processing circuit fabricated in a 0.35um CMOS process is presented. In order to obtain a fast response time, positive feedback loop was implemented. Addition-ally, on-chip timer capacitor was implemented with discharging path made up of DGA n-MOSFET to adjust a pulse width of output signal by controlling an applied voltage. In order to guarantee a TRE tolerance, above-mentioned positive feedback loop was designed with common-source configuration of p-MOSFETs. In addition, dummy MOSFETs are connected to vulnerable nodes to compensate a photocurrent generated by TRE. All pull down networks used in the designed circuit are implemented using DGA n-MOSFET to guarantee a TID toler-ance. The response time of the fabricated chip was 12.2ns. TID and TRE tolerance was greater than 1.14Mrad(Si) and 1.9×$10^7$rad(Si)/s, respectively.