Wireless communication systems have been studied to increase communication speed using a higher order modulation scheme. In addition, the increasing demand for high speed wireless data communications according to consumer requirements has led to extensive research into the millimeter wave (mm-Wave) and the sub-THz bands. In order for a wireless communication
system to achieve data rates of 100 Gbps over a few Gbps, it is necessary to use a high-order modulation method and a wideband characteristic in the sub-THz. Therefore, this paper is about CMOS power amplifiers (PAs) design for 100 Gbps chip-to-chip wireless communication system based on sub-THz band.
The proposed sub-THz CMOS PA for chip-to-chip wireless communication consists of two types. First, as a CMOS PA for QPSK wireless chip-to-chip communication, a dual-bias configuration is proposed. This improved both linearity and efficiency at the same time. Second, a pole-controlled wideband CMOS PA for 16-QAM 100Gbps chip-to-chip wireless communication is proposed. The fabricated PA has a high gain performance and a wideband characteristics of about 40 GHz at the same time. The proposed PA is suitable for high-speed chip-to-chip wireless communication as a result of analysis based on measurement results and linearity analysis. We also proposed a possible implementation of sub-THz PA using CMOS process.