(A) 120 GHz gain-boosting low power 16-QAM receiver for chip to chip communication

Abstract

As the electronics industry develops, the demand for device capable of supporting high data rates is increasing. Many chips such as CPUs, graphic cards, memory devices, and displays need data transfer up to several tens of Gbps. The wire interconnection with high data rate results in severe signal attenuation and distortion due to the dielectric loss on the printed circuit board. The repeaters are needed to cover the dielectric loss which degrades energy efficiency. Considering this issue, wireless connections are more attractive than wire connections between devices for high-speed low-power integrated system. In addition, wireless connections also have potential flexibility and versatility in system design. In system design, we use the CMOS process which is easy to integrate with digital circuits and to implement circuit with low power compared with those based on compound semiconductors. In CMOS circuit design, the transistor characteristic (eg. $f_T$ and $f_{max}$) has inferior performance compared with III - V technologies. Many circuit topologies are used to overcome this issue in low noise amplifier design and down conversion mixer design. In addition, we use a 120 GHz center frequency for wide bandwidth and 16-QAM modulation scheme is adopted to achieve high data rate within certain bandwidth. The target communication distance is 5 cm. The required signal-to-noise ratio of $10^{-12}$ bit error rate for 16 QAM modulations is 20 dB in consideration of phase and amplitude mismatch. The building blocks of the proposed receiver are designed to save power consumption for energy efficiency. In receiver design, direct conversion architecture is determined for wide bandwidth and low power receiver. But, the DC offset phenomenon occurs to direct conversion receiver due to LO leakage at the down conversion mixer. This problem can be somewhat relieved by inserting DC offset cancellation circuit after down conversion mixer. The challenging issues of direct conversion architecture are to obtain high gain in low noise amplifier and to generate a large LO signal from voltage controlled oscillator, especially, at sub-THz frequency due to transistor characteristic of 65 nm CMOS process. To cover these problems, a new topology is proposed to improve gain and save power consumption of the low noise amplifier. In addition, a novel technique is adopted to achieve a high conversion gain in down conversion mixer design with low LO power operation which will reduce power consumption of LO chain. Secondly, the channel analysis of 120 GHz frequency is performed to verify the channel characteristic using Y-shaped antenna which is appropriate for on-board wireless communication. Finally, system link budget including the channel characteristic is calculated to clarify the specification of building blocks for the receiver. The receiver consists of an LNA, an active balun, a down-conversion mixer, a quadrature injection locked oscillator (QILO), and a baseband amplifier. First, the low noise amplifier has six stages and each stage consists of combined cascode topology and common source topology to achieve high gain and save power consumption. In order to enhance the 3dB bandwidth, a two-center frequency technique and inductive feedback technique are used. Second, the down conversion mixer was designed to achieve a high conversion gain by using gain-boosted current bleeding with low LO power operation which will reduce power consumption of LO chain. Third, an active balun is used to reduce insertion loss and minimize the chip area. The issues of design an active balun is to minimize amplitude mismatch and phase mismatch between in-phase signal and out-of-phase signal. The gain for the in-phase and out-of-phase have been balanced by controlling the current though the in-phase path and out-of- phase path to mitigate gain difference. The output inductance and transmission line were used to optimize phase difference be-tween in-phase port and out-of-phase port using 3D EM simulator. Fourth, the QILO uses sub-harmonically injection locked quadrature oscillator as a frequency tripler for D-Band QAM receiver. Sub-harmonically injection topology guarantees to get low phase noise performance from the relatively low-frequency signal source. And injection locked quadrature oscillator can generate sub-THz high output power with maintaining good I/Q phase imbalance. Finally, the issues of design a baseband amplifier is to obtain high gain and wide bandwidth. Cross-coupled capacitors were adopted to broaden the bandwidth and a DC offset cancellation circuit is inserted to overcome the DC offset issue of direct conversion architecture. After all verification process from single chip to a MMIC level, the receiver is fabricated using a TSMC 65 nm CMOS process. The presented receiver achieved a high conversion gain of 27.5 dB at the I and Q paths with an LO power of -10 dBm with very low power. The minimum noise figure was 12.7 dB at IF frequency of 4 GHz and the noise figure of the receiver was less than 16.5 dB within the 3 dB bandwidth. The maximum amplitude mismatch between the I channel and Q channel is 3 dB within a 3 dB bandwidth and the minimum and maximum phase differences between the I channel and Q channel were 0.2° and 3.7°, respectively. The measured output 1 dB compression point was -5 dBm. The receiver occupies only $3.06 mm^2$ including all pads and consumes 174 mW. The proposed receiver is fully expected to be appropriate for high-speed chip-to-chip communication based on the channel analysis and the measurement results. This work makes a substantial contribution towards the realization of using CMOS technology for chip-to-chip communication with very low power.