Advanced optimization techniques of LDPC decoding architecture for NAND flash memory systems낸드 플래시 메모리 시스템을 위한 LDPC 복호화기의 고급 최적화 기법

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The design of error correction system is very important because NAND flash memory has more error than the previous one because of recent miniaturization of process and increase of stored information. Although the BCH decoder is mainly used as an error correction code for protecting the existing NAND flash memory, there is a disadvantage that the hardware complexity becomes very high in order to fix many errors. In order to overcome this problem, LDPC codes, which show good error correction performance while decoding by a relatively simple operation, are gradually replacing BCH codes. One of the important characteristics of the NAND flash channel is that the error rate is very low at the beginning of use, but the error rate increases rapidly after a certain period of use. Therefore, it is reasonable to use low-level error correction using light information at the beginning of the use and to use the year information at the end of the use period. In this dissertation, we propose a hardware architecture that improves the algorithms using semantic and continuous information. In this dissertation, we propose a method of inverting several bits simultaneously under certain conditions based on the size information and experimentally proved that it has the effect of increasing the performance. In addition, the performance of the information decoding performance is further improved by using a method of finer granularity of the algorithm of the information-based algorithm. In order to overcome the complexity of circuit implementation, we proposed a memory - based structure by analyzing the dependency in the decoding process. In addition, since it is necessary only when the error correction of the soft information is failed and the error correction of the soft information is failed, the method of significantly reducing the processing speed of the soft information error correction circuit and greatly reducing the total complexity is proposed and implemented. If the constructed LDPC code achieves a good error-correcting performance, more efficient system can be realized with few hardware resources. In order to improve the conventional code construction method based on local search, a novel LDPC code construction method based on simulated annealing is proposed to optimize the code globally. The proposed optimization method experimentally confirmed that can generate the globally optimized code which has better error-correcting capability than the code generated by the conventional method.
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2018
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2018.2,[v, 76 p. :]

Keywords

Error-correcting codes▼aLDPC codes▼aVLSI decoding architecture▼asimulated annealing▼aoptimization methods; 오류 정정 부호▼aLDPC 부호▼aVLSI 복호기 구조▼aSimulated Annealing▼a최적화 기법

URI
http://hdl.handle.net/10203/265197
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=867926&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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