Low-power low-noise CMOS image sensor using noise-shaping SAR ADC with delta-readout algorithm델타-리드아웃 및 노이즈 쉐이핑 기법의 축차 비교형 데이터 변환기를 이용한 저전력 저잡읍 CMOS 이미지 센서

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dc.contributor.advisorRyu, Seung-Tak-
dc.contributor.advisor류승탁-
dc.contributor.authorHwang, Sun-Il-
dc.date.accessioned2019-08-25T02:44:54Z-
dc.date.available2019-08-25T02:44:54Z-
dc.date.issued2019-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=842393&flag=dissertationen_US
dc.identifier.urihttp://hdl.handle.net/10203/265179-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.2,[iv, 46 p. :]-
dc.description.abstractThis paper presents a CMOS image sensor (CIS) utilizing a noise-shaping successive-approximation register analog-to-digital converter (NS SAR ADC) incorporating the delta-readout scheme. While the NS SAR ADC with a proposed Two-tap passive FIR filter improves effective resolution, the delta-readout scheme reduces its power consumption. A prototype 1920 × 1440 pixel CIS was fabricated in a 90 nm CIS process. A single-channel readout SAR ADC occupying an area of 22.4 μm × 715 μm was implemented for reading out 16 columns of pixel array, consuming 437 μW. Owing to the proposed noise-shaping SAR ADC with oversampling ratio (OSR) of 16, this work achieves a noise-reduction of 14 dB compared with the noise of a conventional SAR ADC. The delta-readout reduces the power consumption of the SAR ADC by 10 % due to the high hit-rate of the Full HD image format. The measured differential nonlinearity (DNL) of the ADC is +0.77/-0.54 LSB and the integral nonlinearity (INL) is +0.81/-0.5 LSB. The prototype CIS consumes a total power of 64 mW, and achieves a dynamic range (DR) of 66.5 dB and a figure-of-merit (FoM) of 127 μV·nJ at a data rate of 138 Mpixels/s. In order to improve the noise-shaping characteristic, a digital integrator was used instead of an opamp-based analog integrator as a loop filter. This greatly reduces the power consumption of the A/D converter and lowers the linearity requirement of the loop filter. Here, a Two-tap FIR filter and a four-input comparator were used to achieve additional noise-shaping effects. Schematic simulations of the proposed NS SAR ADC operating at 10-bit 4.3 M/s at 16 OSR yielded SFDR and SNDR of 82.1 dB and 77 dB, respectively.-
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectCMOS image sensor (CIS)▼abio health care device▼aoversampling▼anoise-shaping successive approximation register analog-to-digital converter (SAR ADC).-
dc.subjectCMOS 이미지 센서▼a바이오 건강 관리 장치▼a오버샘플링▼a노이즈-쉐이핑 축자 비교형 데이터 변환기-
dc.titleLow-power low-noise CMOS image sensor using noise-shaping SAR ADC with delta-readout algorithm-
dc.title.alternative델타-리드아웃 및 노이즈 쉐이핑 기법의 축차 비교형 데이터 변환기를 이용한 저전력 저잡읍 CMOS 이미지 센서-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN325007-
dc.description.department한국과학기술원 :전기및전자공학부,-
dc.contributor.alternativeauthor황선일-
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