Readout circuits that compensate for temperature or temporal drift effects of the phase-change memory = 상 변화 메모리의 온도 또는 시간차 드리프트 효과를 보상하기 위한 판독 회로

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At first, this paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 μm-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 W at 13 Mcells/sec conversion rate at 1.2 V supply. Next, this paper presents a reference-free readout method for phase change memory (PCM) that compensates for the temperature drift of the cell resistance. The proposed method reconfigures the sense amplifier array into flash ADCs in order to extract the optimum decision threshold for the given temperature from the distribution of the data output therefrom. The resolution of the reconfigured flash ADC, the number of flash ADCs for data averaging, and the required number of samples are determined for a target bit-error rate of 1ppm. The proposed sense amplifier (SA) drives a bit-line (BL) rapidly with switchable current sources. A proof-of-concept prototype chip is fabricated via the 180nm CMOS process. A single-channel readout path occupies 137 x 27 $μm^2$ and consumes 305μW under a 3.3V supply, with readout latency less than 100ns.
Ryu, Seung-Takresearcher류승탁researcher
한국과학기술원 :전기및전자공학부,
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학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.2,[iv, 50 p. :]


Logarithmic ADC▼amulti-level cell memory▼aresistance readout circuit▼atwostep ADC▼aphase-change memory (PCM)▼a3D-cross point structure▼aovonic threshold switch (OTS)▼atemperature drift▼atemperature-dependency-compensating readout scheme▼asense amplifier (SA); 로그방식의 아날로그-디지털 변환기▼a다단계 메모리 셀▼a저항 판독 회로▼a두 단계 아날로그-디지털 변환기▼a상 변환 메모리▼a3차원 교차 구조▼a오보닉 임계 스위치▼a온도 드리프트▼a온도 의존성 보상 판독 회로▼a감지 증폭기

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