Low data overhead and noise tolerant digital clock and data recovery circuits for intra-panel interface

Abstract

The increased popularity of high resolution display and high color depth in the intra-panel interface has led to the increase of data rates for pixel data communication. Furthermore, the bezel width becomes narrower to reduce the number of signal lines and source driver ICs at the cost of the high data rates. The development of high data transmission performance has been fraught with difficulty for robustness in the intra-panel interface. A clock and data recovery circuit (CDR) is the most critical block under noise conditions in the source driver IC. A CDR based on a delay-locked loop (DLL) is widely used in the intra-panel interface because of its simplicity and area efficiency. However, DLL-based CDRs suffer from a limitation of data transmission performance: large data overhead for the reliable clock extraction. While a small number of the data overhead are preferred for high throughput, a large number of the data overhead with the DLL-based CDRs are required for robustness to variations of the clock extraction, reducing the effective data rates. Furthermore, as data rates increase to meed the trends, timing margin for the clock extraction is reduced, causing poor BER performance. To address the trade-off, a CDR based on a phase-locked loop (PLL) gains popularity since it can extract clock information from data stream without an unstable clock extraction unit. However, PLL-based CDRs cannot be easily utilized in practical systems due to power noise sensitivity of an oscillator and a large area consumption of an analog loop filter. In this dissertation, several schemes are presented to apply a PLL-based CDR to the intra-panel interface and achieve good jitter performance under various noise conditions. First, a PLL-based CDR with the time-dithered delta-sigma modulator (TDDSM) is proposed to exploit hybrid dithering of output data bit and update clock of the DSM. The sampling period dithering enhances digitally-controlled oscillator (DCO) resolution by using a simple dual modulus divider. Furthermore, the resolution improvement obviates the large number of input bits for the DSM, resulting in the removal of the low-pass filter and reducing jitter generation. The proposed TDDSM is incorporated in the digital loop filter with the low power and area penalties. Then, a PLL-based CDR with supply-insensitive DCO is proposed, which should achieve reliable performance. The differential capacitive coupling and RC time constant techniques are presented to enlarge the effective capacitance and widen the frequency tuning range under large supply fluctuation. By utilizing the coupling network, the CDR architecture has the flexibility to control DCO free-running frequency. A bias generator which controls effective capacitance and RC time constant is also proposed with low and area penalties. Lastly, PLL-based CDRs with pattern-filter merged phase detectors are proposed. The schemes are applied to two types of phase detectors - bang-bang phase detector (BBPD) and phase frequency detector (PFD) to lower output clock jitter. A simple modification of exclusive-or (XOR) gates in the BBPD and a feed-forward manner for the PFD prevent the worst-case data patterns for inter-symbol interference from updating phase information. Moreover, transceivers with simple encoding and decoding schemes are also presented for low level of electro-magnetic interference radiation. Pseudo-random binary sequence generator (PRBS) scrambling and descrambling techniques operating at low frequency are presented with low power consumption. To limit the maximum run-length of the encoded data, the inversion of 2-UI previous bit is introduced as an embedded clock with only 1-bit data overhead. With all of the techniques, flexible and reliable CDRs are achieved with low area and power penalties for intra-panel system.