멀티 코어 시스템 및 멀티 코어 시스템의 작업 스케줄링 방법 processor throttling 기법을 활용한 processor power-gating 구조 및 방법

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A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.
Assignee
KAIST, Samsung Electronics Co., Ltd.
Country
EI
Issue Date
2019-04-24
Application Date
2014-05-22
Application Number
14169487.7
Registration Date
2019-04-24
Registration Number
2808789
URI
http://hdl.handle.net/10203/264160
Appears in Collection
EE-Patent(특허)
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