A Low-power, Mixed-mode Neural Network Classifier for Robust Scene Classification

Cited 15 time in webofscience Cited 12 time in scopus
  • Hit : 719
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorLee, Kyuhoko
dc.contributor.authorPark, Junyoungko
dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2019-05-10T05:30:21Z-
dc.date.available2019-05-10T05:30:21Z-
dc.date.created2019-05-10-
dc.date.created2019-05-10-
dc.date.created2019-05-10-
dc.date.issued2019-02-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.1, pp.129 - 136-
dc.identifier.issn1598-1657-
dc.identifier.urihttp://hdl.handle.net/10203/261852-
dc.description.abstractA low-power neural network classifier processor is proposed for real-time mobile scene classification. It has analog-digital mixed-mode architecture to save power and area while preserving fast operation speed and high classification accuracy. Its current-mode analog datapath replaces massive digital computations such as multiply-accumulate and look-up table operations, which saves area and power by 84.0% and 82.2% than those of digital ASIC implementation. Moreover, the processor integrates a multi-modal and highly controllable radial basis function circuit that compensates for the environmental noise to make the processor maintain high classification accuracy despite of temperature and supply voltage variations, which are critical in mobile devices. In addition, its reconfigurable architecture supports both multi-layer perceptron and radial basis function network. The proposed processor fabricated in 0.13 mu m CMOS process occupies 0.14 mm(2) with 2.20 mW average power consumption and attains 92% classification accuracy.-
dc.languageEnglish-
dc.publisherIEEK PUBLICATION CENTER-
dc.titleA Low-power, Mixed-mode Neural Network Classifier for Robust Scene Classification-
dc.typeArticle-
dc.identifier.wosid000465139300016-
dc.identifier.scopusid2-s2.0-85063538471-
dc.type.rimsART-
dc.citation.volume19-
dc.citation.issue1-
dc.citation.beginningpage129-
dc.citation.endingpage136-
dc.citation.publicationnameJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.identifier.doi10.5573/JSTS.2019.19.1.129-
dc.identifier.kciidART002437958-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorLee, Kyuho-
dc.contributor.nonIdAuthorPark, Junyoung-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorMixed-mode SoC-
dc.subject.keywordAuthorclassifier-
dc.subject.keywordAuthorneural network processor-
dc.subject.keywordAuthormulti-layer perceptron-
dc.subject.keywordAuthorradial basis function network-
dc.subject.keywordPlusIMPLEMENTATION-
dc.subject.keywordPlusENGINE-
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 15 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0