Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 28
  • Download : 0
As the number of datasets processed in computing systems has increased in recent years, there is growing demand for high capacity main memory subsystems. However, further increases in the capacity of conventional DRAM-based main memory systems have stalled due to scaling limitations. Recent studies have shown that PCM, which can provide greater capacity than DRAM, is emerging as a candidate for high capacity memory. However, PCM suffers from problems related to the thermal mechanisms employed for storing data. The Write Disturbance (WD) phenomenon occurs when the thermal mechanisms of the PCM severely damage the data reliability of proximate cells. WD in PCM has become more significant below 20nm. In this paper, we propose Sparse-Insertion Write Cache (SIWC), a practical, low-cost approach to mitigate WD errors. In PCM, repeated writes gradually degrade the validity of data in neighboring cells. SIWC uses a private write cache for the PCM write data to prevent repeated writes to the same address. The sparse-insertion technique can reduce cache eviction and minimize increases in the total write count. Our experimental results show that SIWC effectively reduces repeated writes and reduces the number of WD-vulnerable addresses across a wide range of applications.
Publisher
IEEE COMPUTER SOC
Issue Date
2019-05
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPUTERS, v.68, no.5, pp.752 - 764

ISSN
0018-9340
DOI
10.1109/TC.2018.2881137
URI
http://hdl.handle.net/10203/261607
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0