DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Hu-ung | ko |
dc.contributor.author | Lee, Seongjing | ko |
dc.contributor.author | Kim, Jae-woon | ko |
dc.contributor.author | Won, Youjip | ko |
dc.date.accessioned | 2019-04-19T05:30:12Z | - |
dc.date.available | 2019-04-19T05:30:12Z | - |
dc.date.created | 2019-04-19 | - |
dc.date.issued | 2015-06 | - |
dc.identifier.citation | IEICE ELECTRONICS EXPRESS, v.12, no.12 | - |
dc.identifier.issn | 1349-2543 | - |
dc.identifier.uri | http://hdl.handle.net/10203/261151 | - |
dc.description.abstract | In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core. | - |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | Parallelizing SHA-1 | - |
dc.type | Article | - |
dc.identifier.wosid | 000358128300009 | - |
dc.identifier.scopusid | 2-s2.0-84933045045 | - |
dc.type.rims | ART | - |
dc.citation.volume | 12 | - |
dc.citation.issue | 12 | - |
dc.citation.publicationname | IEICE ELECTRONICS EXPRESS | - |
dc.identifier.doi | 10.1587/elex.12.20150371 | - |
dc.contributor.localauthor | Won, Youjip | - |
dc.contributor.nonIdAuthor | Lee, Hu-ung | - |
dc.contributor.nonIdAuthor | Lee, Seongjing | - |
dc.contributor.nonIdAuthor | Kim, Jae-woon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | cryptography | - |
dc.subject.keywordAuthor | Field-Programmable Gate Array (FPGA) | - |
dc.subject.keywordAuthor | hardware implementation | - |
dc.subject.keywordAuthor | hash functions | - |
dc.subject.keywordAuthor | Secure Hash Algorithm (SHA) | - |
dc.subject.keywordPlus | IMPLEMENTATION | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | FPGAS | - |
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