Parallelizing SHA-1

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In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2015-06
Language
English
Article Type
Article
Citation

IEICE ELECTRONICS EXPRESS, v.12, no.12

ISSN
1349-2543
DOI
10.1587/elex.12.20150371
URI
http://hdl.handle.net/10203/261151
Appears in Collection
EE-Journal Papers(저널논문)
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