Low delay-power product current-mode multiple valued logic for delay-insensitive data transfer mechanism

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Conventional delay-in sensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-mu m CMOS technology. Simulation results with wire lengths of 4 mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2005-05
Language
English
Article Type
Article
Keywords

CIRCUITS; DESIGN

Citation

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E88A, pp.1379 - 1383

ISSN
0916-8508
DOI
10.1093/ietfec/e88-a.5.1379
URI
http://hdl.handle.net/10203/255882
Appears in Collection
GT-Journal Papers(저널논문)
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