Asynchronous multiple-issue on-chip bus with in-order/out-of-order completion

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A multiple-issue on-chip bus of a layered architecture in a Globally Asynchronous Locally Synchronous (GALS) design style, supporting in-order/out-of-order completion, is proposed in this letter. The throughput of the proposed on-chip bus is increased by 31.3% and 34.3%, while power consumption overhead is only 6.76% and 3.98%, respectively, as compared to an asynchronous single-issue on-chip bus.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2005-12
Language
English
Article Type
Article
Citation

IEICE TRANSACTIONS ON ELECTRONICS, v.E88C, no.12, pp.2395 - 2399

ISSN
0916-8524
DOI
10.1093/ietele/e88-c.12.2395
URI
http://hdl.handle.net/10203/255877
Appears in Collection
GT-Journal Papers(저널논문)
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