NearZero: An Integration of Phase Change Memory with Multi-Core Coprocessor

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Multi-core based coprocessors have become powerful research vehicles to analyze a large amount of data. Even though they can accelerate data processing by using a hundred cores, the data unfortunately exist on an external storage device. The separation of computation and storage introduces redundant memory copies and unnecessary data transfers over different physical device boundaries, which limit the benefits of coprocessor-accelerated data processing. In addition, the coprocessors need assistance from host-side resources to access the external storage, which can require additional system context switches. To address these challenges, we propose NearZero, a novel DRAM-less coprocessor architecture that precisely integrates a state-of-the-art phase change memory into its multi-core accelerator. In this work, we implement an FPGA-based memory controller that extracts important device parameters from real phase change memory chips, and apply them to a commercially available hardware platform that employs multiple processing elements over a PCIe fabric. The evaluation results reveal that NearZero achieves on average 47 percent better performance than advanced coprocessor approaches that use direct I/Os (between storage and coprocessors), while consuming only 19 percent of the total energy of such advanced coprocessors.
Publisher
IEEE COMPUTER SOC
Issue Date
2017-07
Language
English
Article Type
Article
Citation

IEEE COMPUTER ARCHITECTURE LETTERS, v.16, no.2, pp.136 - 140

ISSN
1556-6056
DOI
10.1109/LCA.2017.2694828
URI
http://hdl.handle.net/10203/251535
Appears in Collection
EE-Journal Papers(저널논문)
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