Design and Measurement of a Novel On-Interposer Active Power Distribution Network for Efficient Simultaneous Switching Noise Suppression in 2.5-D/3-D IC

Abstract

In this paper, we first propose and demonstrate a novel on-interposer active power distribution network (PDN) scheme to efficiently suppress simultaneous switching noise (SSN) in a 2.5-D/3-D integrated circuit (IC). The on-interposer active PDN can change the PDN impedance by controlling on-interposer decoupling capacitors. The SSN in a 2.5-D/3-D IC is suppressed by optimal control of the on-interposer active PDN scheme. The active interposer is a silicon interposer including active circuits in its silicon substrate to enhance the electrical performance of the 2.5-D/3-D IC. A test interposer of the proposed on-interposer active PDN is fabricated with a 0.18-mu m CMOS process and assembled on a printed circuit board for measurement and analysis. The active circuits of the proposed scheme and hierarchical PDN are modeled with a distributed RLGC-lumped model for fast simulation. The modeling of the proposed scheme is experimentally verified in the frequency and time domains. We successfully demonstrate that an optimum on-interposer decoupling capacitance for the minimized SSN peak-to-peak voltage was obtained by using the proposed scheme. The proposed scheme efficiently suppressed the SSN in 2.5-D/3-D IC by preventing the SSN generation at antiresonance of the hierarchical PDN. In addition, the proposed scheme is compared with a conventional passive PDN scheme, and the maximum ratio of SSN suppression against the conventional scheme was 17.2%.