Fluorine Effects Originating from the CVD W Process on Charge-Trap Flash Memory Cells

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dc.contributor.authorMoon, Jung Minko
dc.contributor.authorLee, Tae Yoonko
dc.contributor.authorAhn, Hyunjunko
dc.contributor.authorLee, Tae Inko
dc.contributor.authorHwang, Wan Sikko
dc.contributor.authorCho, Byung-Jinko
dc.date.accessioned2019-01-23T06:55:06Z-
dc.date.available2019-01-23T06:55:06Z-
dc.date.created2018-11-28-
dc.date.created2018-11-28-
dc.date.created2018-11-28-
dc.date.created2018-11-28-
dc.date.created2018-11-28-
dc.date.issued2019-01-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.1, pp.378 - 382-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/250123-
dc.description.abstractThe fluorine (F) effect originating from the chemical vapor deposited (CVD) tungsten (W) process on charge-trap flash memory devices was systematically investigated, and the CVD-W memory was compared with physical vapor deposited (PVD) W memory. The residual F in the CVD-W diffused into Al 2 O 3 and Si 3 N 4 layers, generating shallow charge-trapping sites in each layer. These generated charge-trapping sites were considered to be responsible for the fast-erase and poor-retention characteristics at room temperature in the CVD-W compared to the related characteristics in the PVD-W memory. The generation of charge-trapping sites caused by the residual F in each layer was also supported by the trap density calculation in the Si 3 N 4 and constant current stress test for the Al 2 O 3 layer.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleFluorine Effects Originating from the CVD W Process on Charge-Trap Flash Memory Cells-
dc.typeArticle-
dc.identifier.wosid000454333500048-
dc.identifier.scopusid2-s2.0-85056743641-
dc.type.rimsART-
dc.citation.volume66-
dc.citation.issue1-
dc.citation.beginningpage378-
dc.citation.endingpage382-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2018.2873693-
dc.contributor.localauthorCho, Byung-Jin-
dc.contributor.nonIdAuthorLee, Tae Yoon-
dc.contributor.nonIdAuthorHwang, Wan Sik-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorBlocking oxide (BO)-
dc.subject.keywordAuthorcharge retention-
dc.subject.keywordAuthorcharge-trap flash (CTF)-
dc.subject.keywordAuthorcharge-trapping layer (CTL)-
dc.subject.keywordAuthorchemical vapor deposition (CVD)-
dc.subject.keywordAuthorfluorine (F)-
dc.subject.keywordAuthorgate electrode-
dc.subject.keywordAuthormemory device-
dc.subject.keywordAuthorprogram/erase (P/E) speed-
dc.subject.keywordAuthorshallow-level electron-trapping-
dc.subject.keywordAuthortungsten (W)-
dc.subject.keywordAuthortunnel oxide (TO)-
dc.subject.keywordPlusOXIDE-
dc.subject.keywordPlusWF6-
dc.subject.keywordPlusRELIABILITY-
dc.subject.keywordPlusIMPROVEMENT-
dc.subject.keywordPlusNUCLEATION-
dc.subject.keywordPlusTIN-
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