Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops

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The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.
Publisher
ASSOC COMPUTING MACHINERY
Issue Date
2018-08
Language
English
Article Type
Article
Citation

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.23, no.5, pp.61:1 - 61:21

ISSN
1084-4309
DOI
10.1145/3229082
URI
http://hdl.handle.net/10203/248316
Appears in Collection
EE-Journal Papers(저널논문)
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