A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading

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This paper presents a memory-efficient receiver architecture for interleave division multiple access (IDMA). For the iterative multiuser detection, existing IDMA architectures first store all log-likelihood ratios (LLRs) into a memory in an iteration, and then despread them in the following iteration. To store new LLRs in the following iteration without overwriting the previous ones to be despread, the memory needs to be duplicated. The proposed architecture, on the other hand, despreads the LLRs on-the-fly while storing them by immediately processing one LLR per cycle. As a result, the architecture finishes despreading within one iteration and is free of the duplicate memory. Since the hardware complexity and the power consumption of an IDMA receiver are dominated by the memory usage, the proposed architecture is particularly effective in alleviating such measures. Moreover, the proposed architecture mitigates the overall latency slightly, as it is exempted from the additional cycles required to despread in the last iteration. Implementation results demonstrate that the IDMA receivers based on the proposed architecture require 57% bits in memories, occupy only 39% silicon area, and consume only 30% power on average, compared to the latest low-latency architecture.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-11
Language
English
Article Type
Article
Keywords

MULTIPLE-ACCESS; LOW-COMPLEXITY; LOW LATENCY; 5G; IMPLEMENTATION

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.11, pp.3327 - 3337

ISSN
0018-9200
DOI
10.1109/JSSC.2018.2863950
URI
http://hdl.handle.net/10203/246889
Appears in Collection
EE-Journal Papers(저널논문)
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