Energy-efficient Convolution Architecture Based on Rescheduled Dataflow

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This paper presents a rescheduled dataflow of convolution and its hardware architecture that can enhance energy efficiency. For convolution involving a large amount of computations and memory accesses, previous accelerators employed parallel processing elements to meet real-time constraints. Though the previous approaches made a success in implementing complex convolution models, they load the same input features and filter weights from on-chip memories multiple times due to the iterative property of convolution operations, suffering from high energy consumption. To mitigate redundant memory accesses, a novel dataflow is proposed that computes convolution operations incrementally so as to reuse the loaded data as maximally as possible. In addition, several convolution accelerators supporting the rescheduled dataflow are investigated, and qualitative and quantitative analyses are performed to suggest a promising candidate for various convolution models. Simulation results show that the energy efficiency of the proposed accelerator outperforms that of the previous accelerator significantly.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.12, pp.4196 - 4207

ISSN
1549-8328
DOI
10.1109/TCSI.2018.2840092
URI
http://hdl.handle.net/10203/246876
Appears in Collection
EE-Journal Papers(저널논문)
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