DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, Jinwook | ko |
dc.contributor.author | Nam, Gijoon | ko |
dc.contributor.author | Reddy, Lakshmi | ko |
dc.contributor.author | Jiang, Iris Huiru | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2018-09-18T06:37:01Z | - |
dc.date.available | 2018-09-18T06:37:01Z | - |
dc.date.created | 2017-11-29 | - |
dc.date.created | 2017-11-29 | - |
dc.date.issued | 2018-09 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.37, no.9, pp.1825 - 1838 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | http://hdl.handle.net/10203/245664 | - |
dc.description.abstract | This paper presents an incremental timing-driven placement tool, named OWARU. It optimizes timing critical paths through a free space-aware path smoothing: the gates on such paths are relocated to free spaces around the smoothed paths, while incremental static timing analysis is involved to accurately assess timing changes due to the relocation. OWARU is extended to accommodate gate sizing and layer assignment to demonstrate the effectiveness of unified physical synthesis optimizations and incremental placement. The goal is to show that OWARU is an ideal platform for timing closure at later stages of a physical design flow. OWARU is applied on a set of test circuits from 14-nm high-performance commercial microprocessors, which originally failed in timing closure. On average, the worst slack is improved by 63.6%, which corresponds to 5.0% of the clock period; total negative slack is improved by 69.1%. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | OPTIMIZATION | - |
dc.subject | CLOSURE | - |
dc.title | OWARU: free space-aware timing-driven incremental placement with critical path smoothing | - |
dc.type | Article | - |
dc.identifier.wosid | 000442371100009 | - |
dc.identifier.scopusid | 2-s2.0-85035116643 | - |
dc.type.rims | ART | - |
dc.citation.volume | 37 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 1825 | - |
dc.citation.endingpage | 1838 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.identifier.doi | 10.1109/TCAD.2017.2774277 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Nam, Gijoon | - |
dc.contributor.nonIdAuthor | Reddy, Lakshmi | - |
dc.contributor.nonIdAuthor | Jiang, Iris Huiru | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Critical path smoothing | - |
dc.subject.keywordAuthor | physical design | - |
dc.subject.keywordAuthor | placement | - |
dc.subject.keywordAuthor | timing closure | - |
dc.subject.keywordAuthor | timing-driven placement | - |
dc.subject.keywordPlus | OPTIMIZATION | - |
dc.subject.keywordPlus | CLOSURE | - |
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