A Simple SR Gate Driving Circuit With Reduced Gate Driving Loss for Phase-Shifted Full-Bridge Converter

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The phase-shifted full-bridge (PSFB) converter with synchronous rectifier (SR) is one of the most attractive dc-dc converters for the server power supply due to its high power capability and small secondary ripple current with the output inductor. Moreover, it can more reduce the secondary conduction loss by using parallel-connected MOSFETs in SR. However, due to large input capacitance of the parallel-connected MOSFETs in SR, the PSFB converter has large SR gate driving loss, which particularly degrades the light load efficiency. Thus, in this paper, one additional resistor is added to the conventional SR gate driving circuit to recycle the gate driving energy. As a result, the proposed circuit can improve the light load efficiency of the PSFB converter without operation mode change, additional controls, and complex circuits. The most advantage of the proposed circuit is that it is very simple and available to any other SR gate driver IC. The validity of the proposed circuit is confirmed by experimental results from a prototype with 340-400 V input and 12 V/66.66 A output.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-11
Language
English
Article Type
Article
Keywords

LIGHT-LOAD EFFICIENCY; SERVER POWER

Citation

IEEE TRANSACTIONS ON POWER ELECTRONICS, v.33, no.11, pp.9310 - 9317

ISSN
0885-8993
DOI
10.1109/TPEL.2018.2789340
URI
http://hdl.handle.net/10203/245634
Appears in Collection
EE-Journal Papers(저널논문)
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