Fast Low-Comlexity Triple-Error-Correcting BCH Decoding Architecture

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An efficient decoding architecture for triple-error-correcting BCH codes is proposed by utilizing a lookup table (LUT) that stores the roots of the error locator polynomial instead of using the Chien search. Two roots of the polynomial equation are precomputed and stored in the LUT in order to relax the hardware complexity. To relax the complexity further, a new method to compress the LUT is additionally proposed. While a large portion of the LUT is filled with unnecessary information in the previous designs, this work eliminates the redundant information by investigating an algebraic property of the equation. For BCH codes over GF(2¹⁰), the LUT size is reduced to 18 % of the previous work. As a result, the proposed decoding architecture reduces the decoding latency by 38 % and the equivalent gate count by up to 40 % compared to the previous work, achieving a fast low-complexity triple-error-correcting BCH decoder.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-06
Language
English
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.6, pp.764 - 768

ISSN
1549-7747
DOI
10.1109/TCSII.2017.2779139
URI
http://hdl.handle.net/10203/245435
Appears in Collection
EE-Journal Papers(저널논문)
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