(A) 3.2Gbps DLL-based optimized data-recovery transceiver of Data Buffer for DDR4 LRDIMMDDR 4세대 LRDIMM을 위한 데이터 버퍼의 지연 고정 루프를 이용한 최적화된 3.2Gbps의 데이터 복원 송수신기 설계

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As the demand for higher data rate and larger DRAM capacity in recent server memory, DDR memory has been evolved in a variety of ways, and in DDR4, a buffer chip called the Data Buffer (DB) has also been integrated. However, there still remain problems such as multi-drop data transfer paths, PVT variation and cross-talks. In this Master of Science thesis, the proposed transceiver circuit can remove or mitigate these issues. DIMM channel model implemented with HFSS tools provides much precise signal transfer characteristic to de-termine the transceiver circuit specification. The forwarded clock with the delay lock loop (DLL) can track the jitter due to PVT variation on clock path. Based on this clock scheme, an additional sampler which tracks the data edge (clock-data recovery logic) can track the jitter due to that on data path. In addition, the decision feed-back equalizer (DFE) can be used to remove the reflection from the channel and the multi-drop path, and the SNR degradation due to cross-talk can be mitigated by using 3x-Oversample and majority vote based sampler scheme.
Advisors
Bae, Hyeon Minresearcher배현민researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2017.8,[iv, 30 p. :]

Keywords

디램▼a데이터 버퍼▼a지연 고정 루프▼a데이터 가장자리 추적▼a판정 궤환 등화기▼a클록 데이터 복원▼a다중 접속 전달▼a공정-전압-온도 변조▼a누화; DRAM▼aData Buffer▼adelay lock loop▼adata edge tracking▼ajitter▼adecision feedback equalizer▼aclock-data recovery▼amulti-drop transfer▼aPVT variation▼across-talk

URI
http://hdl.handle.net/10203/243362
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=718679&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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