(A) 3.2Gbps DLL-based optimized data-recovery transceiver of Data Buffer for DDR4 LRDIMM

Abstract

As the demand for higher data rate and larger DRAM capacity in recent server memory, DDR memory has been evolved in a variety of ways, and in DDR4, a buffer chip called the Data Buffer (DB) has also been integrated. However, there still remain problems such as multi-drop data transfer paths, PVT variation and cross-talks. In this Master of Science thesis, the proposed transceiver circuit can remove or mitigate these issues. DIMM channel model implemented with HFSS tools provides much precise signal transfer characteristic to de-termine the transceiver circuit specification. The forwarded clock with the delay lock loop (DLL) can track the jitter due to PVT variation on clock path. Based on this clock scheme, an additional sampler which tracks the data edge (clock-data recovery logic) can track the jitter due to that on data path. In addition, the decision feed-back equalizer (DFE) can be used to remove the reflection from the channel and the multi-drop path, and the SNR degradation due to cross-talk can be mitigated by using 3x-Oversample and majority vote based sampler scheme.