Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s

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In this paper, we propose a new on-siliconinterposer passive equalizer for next generation high bandwidth memory (HBM) with 1024 I/O lines and 8-Gb/s data transmission, which is four times higher than the data rate of HBM generation 2. The proposed equalizer meets the three requirements for the implementation of ultra-high bandwidth interface with wide I/O lines: 1) small area; 2) fine pitch; and 3) low power. The proposed equalizer is embedded in a ground plane on an interposer to reduce additional area consumption. By staggering the equalizers in two rows, 7-mu m pitch of the channel can be maintained. The equalizer consumes only 8.24 mW at the data rate of 8 Gb/s since it adopts passive equalization methodology. Robust performance that is independent of insertion location provides design flexibility. The proposed design process for the equalizer helps to reduce manufacturing time and cost. We have verified the performance of the proposed equalizer using simulation and measurement. By applying the proposed equalizer, the eye diagram which was completely closed is successfully open with an eye height of 11.5% VTX, output and an eye width of 57.8% unit interval at a bit-error rate of 10(-12).
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-07
Language
English
Article Type
Article
Keywords

DATA-TRANSMISSION; CHIP; MODEL

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.7, pp.2293 - 2303

ISSN
1549-8328
DOI
10.1109/TCSI.2017.2783762
URI
http://hdl.handle.net/10203/242598
Appears in Collection
EE-Journal Papers(저널논문)
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