Detection of the Interface-Trap Charge Density and Lateral Nonuniformity of Through-Silicon Vias

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Through-silicon via (TSV) technology has emerged as a key component of 3-D integrated circuits. As the integration density in a package increases, the nonlinear metal-oxide-semiconductor (MOS) capacitance in TSVs has a greater effect on the electrical performance of the devices. Imperfections due to the deposition of a dielectric layer are important factors which can change the characteristics of the MOS capacitance. This letter presents a method by which to detect the interface-trap charge density D-it and lateral nonuniformity (LNU) of imperfections in TSVs. The results of an analysis of a measured sample define Dit and LNU at the dielectric-semiconductor interface and demonstrate that the presence of LNU can be established by a negative D-it.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-05
Language
English
Article Type
Article
Keywords

PERFORMANCE ANALYSIS; MOS CAPACITORS

Citation

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.28, no.5, pp.422 - 424

ISSN
1531-1309
DOI
10.1109/LMWC.2018.2822731
URI
http://hdl.handle.net/10203/242413
Appears in Collection
GT-Journal Papers(저널논문)
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