A discrete-time (DT) receiver for software-defined radio (SDR) applications is presented. The receiver chain includes a wideband LNA and high linearity current commutating passive mixers merged with baseband switched-capacitor filters (SCFs) in current mode to simplify analog circuitries and reduce power consumption. An RF transconductor (RF TA) with capacitive-peaking bandwidth extension technique is proposed for the mixers to maximize the operating frequency band of the receiver. Implemented in a 0.18 mu m CMOS process, the proposed receiver achieves a maximum voltage conversion gain of 41.2 dB, minimum NF of 3.8 dB, in-band IIP3 of -9 dBm, and out-of-band IIP3 of -6 dBm, respectively. The receiver operates from 0.7 to 2.4 GHz while dissipating 28-34 mA current from 1.8 V supplies.