Development of process technology for high performance Ge MOSFETs

Abstract

Ge has a big advantage over Si in terms of high electron and hole mobilities, and its low processing temperature makes it easier to integrate with high-k materials. This dissertation presents two approaches to address issues of Fermi level de-pinning at the metal/n-Ge interface and the formation of reliable gate stack considering its thermal instability and electrical performances. In the metal/n+-Ge contact of Ge n-MOSFETs, there is a strong Fermi level pinning neat the valence band edge of Ge bandgap in the metal/Ge contact and this leads a high contact resistivity with high Schottky barrier height as same as its band gap. We demonstrated two kinds of Fermi level de-pinning methods which are the direct deposition of TaN on the Ge surface and self-aligned $Ti/GeO_2/Ge$ contact to form an interfacial $TiO_x$ thermodynamically. These two approaches reduce the Schottky barrier height for electron by a half of Ge band gap. In the gate stack, in order to overcome the limit of conventional thermal growth fabrication process, a plasma oxidation methodology has been purposed to form a $GeO_2$ channel passivation layer on the Ge surface. In addition, to suppress the $GeO_2$ desorption during/after the fabrication, $Y_2O_3$ and AlON capping layers are studied in the light of EOT scalability and gate stack quality. In the case of $Y_2O_3$ passivation, there is a certain scalability limitation below EOT of 1.0nm as a $GeO_2$ capping layer due to the introduction of high trap site density as $Y_2O_3$ thickness below 1.0 nm. AlON is the better choice for $GeO_2$ channel passivated Ge MOSFET with reliable device operation compared with conventional $Al_2O_3/GeO_2$ MOSFETs due to its lower border trap density than $Al_2O_3$.