Low-power 100-gigabit ethernet transceiver IC using stochastic sigma-tracking eye-opening monitor = 확률적 시그마 추적 아이다이어그램 모니터 방법을 이용한 저전력 100 기가비트 이더넷 트랜시버 IC

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This thesis describes a low-power 100-Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40-nm CMOS. The proposed transceiver IC contains a total of four 28 Gb/s transceivers (TRX). Each TRX lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the TRX lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line and quad-rate receiver (RX) and transmitter (TX) schemes without current-mode-logic (CML) gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from $478mV_{ppd}$ to $1.06V_{ppd}$. The proposed receiver employs a continuous time linear equalizer (CTLE) and an one-tap decision feedback equalizer (DFE) to compensate for the channel loss up to 25 dB at the Nyquist rate. The proposed stochastic sigma-tracking eye-opening monitor (SSEOM) accurately detects the BER-related eye opening with a feasible degree of time/area without the use of an external microcontroller. The SSEOM determines the BER-optimal sampling point of data sampler and equalizer coefficients by incorporating a pattern-filtered eye diagram. It also features a background adaptation scheme for robust long-term operation by tracking temperature variations and device aging. The measured RX input sensitivity for a BER of $10^{-12}$ is $19.4mV_{ppd}$. The proposed IC consumes only 0.44 W at 28.0 Gb/s with a BER less than $10^{-15}$ on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25-Gb/s transceivers.
Advisors
Bae, Hyeon-Minresearcher배현민researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2016
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.2,[vi, 45 p. :]

Keywords

Adaptive Equalizer; Clock and data recovery; delay- and phase-locked loop; Eye-opening monitor; Sampling point control; 100 기가비트 이더넷; 트랜시버; 클럭 데이터 복원; 저전력; 적응 등화

URI
http://hdl.handle.net/10203/241994
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=669290&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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