Analysis of local stresses in Si around Cu through-silicon via for 3D integrated circuit

Abstract

Through Silicon Via is one of the key elements of the next generation electronic, microelectromechanical systems (MEMS), and systems with high bandwidth interconnections. However, incorporation of TSVs, where the Cu via is formed via electroplating process and several processing steps at elevated temperatures are implemented, poses a significant challenge in maintaining device reliability due to the stress distribution introduced in silicon. The residual stress from the Cu deposition, thermal stresses from the processing steps at elevated temperatures, and stresses from the deposition of passivating overlayers can all affect the stresses in Si that can unexpectedly result in difference in mobility of the charge carriers. Therefore, finding the keep off zone, where the stress distribution near the Cu via is minimized, is of critical importance. In this work, In this study, local Si stress distribution near Cu TSVs with various via sizes with and without passivation layers were characterized using micro-Raman spectroscopy and compared against finite element modeling and analysis using technology computer-aided design software. Effects of thermal cycling on the local Si stress distribution around Cu TSVs were characterized after depositing transparent $SiO_2$ and SiN thin films (>11 layers) on top of Cu TSVs. Si stresses, which are dependent on TSV size and density, were characterized and discussed from the perspective of the microstructural change in the Cu TSV. This is the first report on using micro Raman method to non-destructively characterize and analyze the stresses in Si as a function of via size then again as a function of processing steps. It should be noted that the Cu TSVs explored in this study is in the range of 4-8 $\mu m$, which is practical dimension for high density 3-D memory packaging, known as high bandwidth memory, that is currently being developed in the industry.