Deuterium (D-2) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (mu) was extracted using the gate transconductance (gm) method. It was found that mu was improved before and after D-2 annealing. The interface trap density (D-it) as well as the oxide trap density (N-ot) in the poly-Si TFTs was quantitatively extracted using both conventional dc I-V characterization and analysis of low frequency noise (LFN). The profile of N-ot along the depth direction was investigated before and after D-2 annealing using LFN characteristics. It was confirmed that D-it as well as N-ot was reduced by the D-2 annealing, resulting in a reduction in power spectral density and variation.