A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling

This paper introduces a high-order continuous-time (CT) delta-sigma modulator (DSM) that applies digital-domain noise coupling (DNC) based on the structural advantages of the successive-approximation register (SAR) analog-to-digital converter (ADC), which makes the implementation of second-order noise coupling very simple. Due to digital-domain implementation as well as the SAR ADC where the key building blocks are embedded for the proposed DNC, compact size and efficient power consumption could be designed. For low circuit noise, a feedback DAC is implemented with a tri-level current-steering DAC. Tri-level data-weight averaging (TDWA) improves the linearity of the DAC. With the proposed DNC and TDWA, a prototype CT DSM fabricated in a 28-nm CMOS achieves a peak 74.4-dB SNDR and an 80.8-dB dynamic range (DR) for a 10-MHz BW with an oversampling ratio of 16, resulting in a Schreier FoMDR of 174.5 dB. The chip area occupies 0.1 mm(2), and the power consumption is 4.2 mW.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-04
Language
English
Article Type
Article; Proceedings Paper
Keywords

EXCESS-LOOP-DELAY; DB-SNDR; NM CMOS; DYNAMIC-RANGE; ADC; BANDWIDTH; MW; COMPENSATION; ENOB

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1139 - 1148

ISSN
0018-9200
DOI
10.1109/JSSC.2017.2778284
URI
http://hdl.handle.net/10203/241418
Appears in Collection
EE-Journal Papers(저널논문)
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