Band bending effect induced by gate voltage on the charge loss behavior of charge trap flash memory devices

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dc.contributor.authorChang, M.ko
dc.contributor.authorHwang, H.ko
dc.contributor.authorJeon, Sanghun.ko
dc.date.accessioned2018-03-21T02:57:00Z-
dc.date.available2018-03-21T02:57:00Z-
dc.date.created2018-03-07-
dc.date.created2018-03-07-
dc.date.issued2010-02-
dc.identifier.citationAPPLIED PHYSICS LETTERS, v.96, no.5-
dc.identifier.issn0003-6951-
dc.identifier.urihttp://hdl.handle.net/10203/240843-
dc.description.abstractWe found that the polarity of the gate voltage (V(g)) during the retention characteristics for a SiO(2)/Si(3)N(4)/Al(2)O(3) (ONA) stack can affect the charge loss direction, due to band bending. Positive V(g) could induce electron de-trapping through Al(2)O(3), while a negative V(g) could induce the same through SiO(2). Consequently, the charge loss rates exhibited a hairpin curve with V(g). We clearly observed that increases of the SiO(2) thickness of the ONA stack induced negative shifts of hairpin curve. This result suggests that the dominant charge loss path could be changed from SiO(2) to Al(2)O(3) by increasing the SiO(2) thickness without V(g).-
dc.languageEnglish-
dc.publisherAMER INST PHYSICS-
dc.subjectRETENTION-
dc.subjectCELLS-
dc.titleBand bending effect induced by gate voltage on the charge loss behavior of charge trap flash memory devices-
dc.typeArticle-
dc.identifier.wosid000274319500047-
dc.identifier.scopusid2-s2.0-76449105842-
dc.type.rimsART-
dc.citation.volume96-
dc.citation.issue5-
dc.citation.publicationnameAPPLIED PHYSICS LETTERS-
dc.identifier.doi10.1063/1.3295697-
dc.contributor.localauthorJeon, Sanghun.-
dc.contributor.nonIdAuthorChang, M.-
dc.contributor.nonIdAuthorHwang, H.-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthoraluminium compounds-
dc.subject.keywordAuthorflash memories-
dc.subject.keywordAuthorsilicon compounds-
dc.subject.keywordPlusRETENTION-
dc.subject.keywordPlusCELLS-
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