Three-Dimensional Integration Approach to High-Density Memory Devices

Cited 17 time in webofscience Cited 0 time in scopus
  • Hit : 27
  • Download : 0
The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically active oxide thin-film transistors (TFTs) combined with memory elements such as vertical NAND and resistive random accessmemory devices. High-mobility [similar to mu(saturation) of 20 cm(2)/(eV . s)] oxide TFTs with amorphous Hf-In-Zn-O performs fairly well as a decoder, a driver, a sense amplifier, and a latch, and the core elements that are required for 3-D logic circuits. With these logic circuit elements, memory density can be considerably increased up to tens of terabits due to the significantly reduced interconnection lines and logic circuit areas in the bottom silicon layer. This approach can serve as a useful strategy for the development of high-density memory devices.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2011-11
Language
English
Article Type
Article
Keywords

THIN-FILM TRANSISTORS; OXIDE SEMICONDUCTORS; NONVOLATILE MEMORY; GRAPHENE; ARRAYS

Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.11, pp.3820 - 3828

ISSN
0018-9383
DOI
10.1109/TED.2011.2165286
URI
http://hdl.handle.net/10203/240824
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 17 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0