Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs

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A highly biased linear current method (HBLCM) for separately extracting source and drain resistance (R-S and R-D) in MOSFETs is proposed. The technique can be applied to a single device by using simple modeling. Compared to other methods, it provides accurate values of R-S and R-D because it considers carrier mobility degradation. The method basically uses linear current versus gate voltage (I-DS-V-GS and I-SD-V-GD) characteristics before and after the source/drain interchange (I-DS and I-SD). Afterward, by using the traditional Y-function and subsequent resistance modeling in a highly biased linear condition, R-S and R-D can be separately extracted. In order to evaluate and verify the accuracy of HBLCM, an external resistor was intentionally connected to a source electrode of a device, and the resulting change in source resistance was detected using the proposed method. Moreover, to demonstrate an application of the proposed method, internal resistance deliberately created by hot-carrier injection (HCI) was linked to a drain electrode, thereby changing drain resistance. The changed drain resistancewas also sensed by the HBLCM. Afterward, the HCI-stressed device was cured by electrothermal annealing driven by Joule heating, and the recovery was again clearly observed using the proposed method.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-02
Language
English
Article Type
Article
Keywords

FIELD-EFFECT TRANSISTORS; SERIES RESISTANCE; STRAINED SI; MOBILITY; PARAMETERS; DEGRADATION; GE

Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.2, pp.419 - 423

ISSN
0018-9383
DOI
10.1109/TED.2017.2783924
URI
http://hdl.handle.net/10203/240199
Appears in Collection
EE-Journal Papers(저널논문)
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