Automatic insertion of airgap with design rule constraints

Abstract

Airgap is a technology that enables air to be used as IMD (inter metal dielectric). It brings about reduced coupling capacitance, which helps reduce circuit delay and power consumption. Airgap is constrained by a number of design rules. Manual insertion of airgap while design rules are all respected is inconvenient and time consuming. We address automatic airgap insertion in this paper, in which the goal is to insert maximum amount of airgap in selected paths (e.g. timing critical paths) while related design rules are all honored. Our approach consists of three steps: (1) layout is decomposed into a set of sublayouts, such that airgap can be inserted in each sublayout independently, (2) each of large sublayouts is further partitioned in heuristic fashion, and (3) airgap insertion in each sublayout (or each partition of sublayout) is performed through ILP (integer linear programming). Experiments indicate that runtime is manageable; the impact of airgap on circuit delay is also demonstrated, e.g 5.6% improvement of worst slack on average of test circuits.