Automatically calibrating frequency features of a phase locked loop고속 개루프 자동 주파수 보정회로를 가지는 위상 고정 루프

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A PLL includes an open-loop automatic frequency calibration circuit. The open-loop automatic frequency calibration circuit includes a frequency detector, first and second sinks, a comparator and a bank selector. The frequency detector generates an up-signal and a down-signal responding to a frequency difference between a first phase difference signal having a phase difference from a reference oscillation signal and the second phase difference signal having a phase difference from a frequency division oscillation signal. The first and second sinks discharge the first and second capacitors respectively responding to the up-signal and the down-signal. The comparator compares voltages of the first and second capacitors. The bank selector selects a bank according to binary search, selects an optimum bank among two banks lastly searched, and outputs a bank selection signal. The voltage-controlled oscillation changes frequency features thereof in response to the bank selection signal.
Assignee
KAIST
Country
US (United States)
Issue Date
2010-05-18
Application Date
2007-05-08
Application Number
11745654
Registration Date
2010-05-18
Registration Number
7719375
URI
http://hdl.handle.net/10203/235140
Appears in Collection
EE-Patent(특허)
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