In order to reduce the two major problems of short-channel effects and limited threshold voltage controllability in submicrometer gate heterostructure FET's (HFET's), a p-i-p+ structure in the buffer is investigated. The p layer is adjacent to the channel and the p+ layer is located fairly far from the channel. This structure lowers the electrostatic potential in the buffer under the channel, which reduces the current in this region. Monte Carlo simulation shows that such a buffer decreases the output conductance in saturation by 80% for a 0.3-mu-m gate delta-doped Modulation Doped FET (MODFET) with n+ self-aligned source and drain regions. The p+ layer has the additional purpose of enabling adjustment of the threshold voltage by way of changing the potential of the p+ layer externally. Our one-dimensional calculations for the modulation-doped AlGaAs/GaAs heterostructures show that a 0.1-V variation of the threshold voltage can be adjusted by a 2-V variation of the back bias when the p+ layer is located 5000 angstrom away from the channel. However, the maximum carrier density n(s max) in the 2-D gas becomes quite limited when high negative bias is applied to the p+ layer or when the distance from the p+ layer to the heterointerface is decreased. This limitation is less severe in delta-doped structures where n(s max) is approximately 70% larger. In Doped Channel HFET (DCHFET) structures, the p+ layer can be brought very close to the n+ doped channel without any important restrictions on n(s max) in the channel. The p layer sheet doping density must also be restricted to approximately 1.5 x 10(12) cm-2 for the MODFET in order to avoid a large reduction of n(s max) Again, this limitation is not important in DCHFET devices. Therefore, use of the p-i-p+ buffer is more advantageous for delta-doped MODFET's than for uniformly doped MODFET' s, and even more so for DCHFET's, where larger charges in the p-i-p+ buffer are required to limit the short channel effects.