Negative capacitance logic device, clock generator including the same and method of operating clock generator 네가티브 커패시턴스 논리 장치, 작동 클록 제너레이터의 동일한 것 및 방법을 포함해 클럭 발생 장치

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A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.
Assignee
한국과학기술원
Country
US (United States)
Issue Date
2016-11-01
Application Date
2015-02-05
Application Number
14614884
Registration Date
2016-11-01
Registration Number
9484924
URI
http://hdl.handle.net/10203/230363
Appears in Collection
EE-Patent(특허)
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