A kind of junctionless vertical gate transistor, including:Active cylinder, the active cylinder from substrate transverse it is prominent, and including the first impurity range, in second impurity range being sequentially formed on of first impurity range and the 3rd impurity range;Gate electrode, the gate electrode is coupled to the side wall of second impurity range;And bit line, the bit line is arranged along the direction intersected with the gate electrode, and each is contacted with first impurity range.First impurity range, second impurity range, the 3rd impurity range include the impurity of identical polar.