A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory

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To improve the reliability of MLC NAND flash memory, this paper presents an energy-efficient high-throughput architecture for decoding concatenated-BCH (CBCH) codes. As the data read from the flash memory is hard-decided in practical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capability and energy efficiency. In the proposed CBCH decoding, the number of on-chip memory accesses consuming much energy is minimized by computing and updating syndromes two-dimensionally. To achieve an area-efficient hardware realization, row and column decoders are unified into one decoder and some syndromes are computed when they are needed. In addition, the decoding throughput is enhanced remarkably by skipping redundant decoding processes. Based on the proposed CBCH decoding architecture, a prototype chip is implemented in a 65-nm CMOS process to decode the (70528, 65536) CBCH code. The proposed decoder provides a decoding throughput of 17.7 Gb/s and an energy efficiency of 2.74 pJ/bit, being vastly superior to the state-of-the-art architectures.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2013-10
Language
English
Article Type
Article
Keywords

ERROR-CORRECTION; POWER

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.10, pp.2531 - 2540

ISSN
0018-9200
DOI
10.1109/JSSC.2013.2275655
URI
http://hdl.handle.net/10203/228481
Appears in Collection
EE-Journal Papers(저널논문)
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